TUSB1210 data sheet, product information and support | TI.com
DWTB: USB High Speed Inter-Chip (HSIC) IP: What is it? And why should I use it?
USB 3.0 PHY IP Core
Canovatech - CT20602
USB 2.0 Device Controller for SoC Designs | Cadence IP
Soft Mixed Signal Corporation USB 2.0 PHY IP Cores
DE10-Advance Hardware Manual revC Chapter5 USB OTG - Terasic Wiki
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
Corigine Unveils First Certified SuperSpeed+ USB 3.1 Gen 2 IP with M31 28nm PHY | audioXpress
USB 2.0 Full High Speed Solution | NXP Semiconductors
ASMedia Demos USB 3.2 Gen 2x2 PHY, USB 3.2 Controller Due in 2019
High Speed Inter-CHIP USB 2.0 PHY | Arasan Chip Systems
Canovatech - CT25201_PHY
PCIe/USB/SATA PHY Appilcation example | Renesas
USB 2.0 Full High Speed Solution | NXP Semiconductors
Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
USB 2.0 PHY Verification
USB 2.0 Solutions | Arasan Chip Systems
Hi-Speed USB interfacing
USB 3.0/2.0 Combo PHY IP for SoC Designs | Cadence IP
The USB 2.0 Device IP core | Arasan Chip Systems
USBPHYC internal peripheral - stm32mpu
Figure 2 from Verilog synthesis of USB 2.0 full-speed device PHY IP | Semantic Scholar
Archimago's Musings: MEASUREMENTS: Computer USB port noise, USB hubs and the 8kHz PHY Microframe Packet Noise
Having trouble getting USB PHY to work with STM32 : r/embedded
The Next-Generation Interconnect | Mouser
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HSIC USB 2.0 PHY IP
